Chip Gallery
A collection of physical-design layouts from my research in memory-centric AI accelerators.
ICCAD 2025 · PIM-NoC architecture
LEAP
A scalable processing-in-memory network-on-chip accelerator for LLM inference. The layout illustrates a 2 × 2 macro array with PIM processing elements, scratchpads, and integrated routers, accompanied by area breakdowns.
ICCAD 2026 · Heterogeneous memory-centric AI
OmniAcc
A heterogeneous LLM accelerator integrating in-memory computing, near-memory computing and reconfigurable nonlinear processing. The layout highlights IMC tiles, local scratchpads, router regions, and dedicated nonlinear-processing columns.