{ "version": "1.0.0", "asOf": "2026-10-23", "editorialScope": "Verified and announced memory-centric compute products, plus explicitly tagged enabling memories. No geopolitical analysis.", "companies": [ { "name": "Yizhu Technology", "native": "亿铸科技", "city": [ "Suzhou", "Shanghai", "Hangzhou", "Chengdu", "Changsha" ], "origin": "No specific university spin-off established in reviewed sources.", "funders": [ "盛视科技 (Shengshi Technology)" ], "website": "https://www.yizhu-tech.com/", "msources": [ "https://www.yizhu-tech.com/about.php", "https://www.yizhu-tech.com/newsv.php?id=124" ], "note": "The vendor now emphasizes all-digital 3D DRAM. Historical RRAM descriptions should not be used as its current product architecture.", "id": "yizhu-technology", "products": [ "yizhu-technology-3d-dram-digital-cim-family-yica" ], "category": "3D / near-memory" }, { "name": "MemSilicon", "native": "铭芯启睿", "city": [ "Beijing" ], "origin": "Incubated from the Chinese Academy of Sciences Institute of Microelectronics; Liu Ming research team. The company lists Prof. Liu Qi (Fudan University) among its co-founders.", "funders": [ "Lenovo Capital", "Xiaomi Ventures", "Bosch Ventures", "miHoYo", "GigaDevice" ], "website": "https://memsilicon.com/", "msources": [ "https://memsilicon.com/zzjg", "https://www.leiphone.com/", "https://capital.lenovo.com/news/detail/id/1085/s/1.html", "https://m.leiphone.com/category/chips/56PWzwTNdteGx04q.html" ], "note": "2026 MountTai is an RRAM memory device, not a verified CIM MAC engine. LPU compute is a separate ongoing development.", "id": "memsilicon", "products": [ "memsilicon-mounttai-2026" ], "category": "Memory enabler" }, { "name": "MicroNanoCore", "native": "微纳核芯", "city": [ "Hangzhou", "Wuxi", "Hefei", "Beijing", "Shanghai", "Shenzhen" ], "origin": "Incubated by the Advanced Institute of Information Technology, Peking University (Zhejiang). Founder and chief scientist Ye Le (叶乐) is an associate professor and PhD supervisor at Peking University's School of Integrated Circuits, and deputy director/IoT Center director at the institute. His research includes CIM AI chips, 3D integrated architectures and mixed-signal circuits. The academic research lineage includes the Peking University Ru Huang–Ye Le (黄如—叶乐) group; the company also reports joint research with Ru Huang's team on 3D-TokSIM. Institutional incubation is explicitly documented.", "funders": [ "Xiaomi", "Lenovo Capital", "Luxshare Precision", "GigaDevice", "China Mobile investment arm", "Sequoia China" ], "website": "https://nanocorechip.com/", "msources": [ "https://nanocorechip.com/index/news/detail/index?id=51", "https://ic.pku.edu.cn/szdw/zzjs/jcdlsjx1/yl/", "https://nanocorechip.com/index/news/detail/index?id=15", "https://nanocorechip.com/index/news/detail/index?id=23", "https://nanocorechip.com/index/news/detail.html?id=3", "https://nanocorechip.com/index/aboutus/company.html", "https://www.ccf.org.cn/Media_list/adl/2026-07-30/919088.shtml", "https://nanocorechip.com/", "https://nanocorechip.com/index/news/detail/index?id=7" ], "note": "University incubation and founder affiliation confirmed by company and Peking University. Founder/Chief Scientist is the independently documented company title; CTO is not verified. Reported office locations are not all individually verified as R&D labs. Earlier non-CIM chip shipments do not establish that the new 3D-CIM product family has shipped.", "id": "micronanocore", "products": [ "micronanocore-3d-cim-pcie-cim-lp-cim" ], "category": "3D / near-memory", "people": [ { "name": "Ye Le · 叶乐", "role": "Founder & Chief Scientist (company and 2026 conference sources); Peking University School of Integrated Circuits associate professor, PhD supervisor; deputy director of Zhejiang's PKU Advanced Institute of Information Technology. CTO title was user-reported but not independently confirmed in reviewed sources." } ] }, { "name": "WITMEM", "native": "知存科技", "city": [ "Beijing", "Hangzhou", "Shanghai", "Tianjin", "Xi'an", "Shenzhen" ], "origin": "Founders have Peking University, UCLA and UCSB research backgrounds. Peking University–WITMEM joint CIM laboratory established in 2024; a joint lab is not evidence of formal university spin-off.", "funders": [ "SDIC Venture Capital", "Shuimu Chunjin Capital" ], "website": "https://www.witmem.com/", "msources": [ "https://www.witmem.com/about.php", "https://en.witmem.com/newsshow.php?id=977", "https://www.xinhuanet.com/tech/20230106/ec33e33e368740729d06a4dc093ab768/c.html" ], "note": "WTM2101 achieved commercial manufacturing; WTM-8 has separately been described by the company as trial-manufactured.", "id": "witmem", "products": [ "witmem-wtm2101", "witmem-wtm-8" ], "category": "Analog CIM" }, { "name": "REEXEN", "native": "九天睿芯", "city": [ "Shenzhen", "Chengdu", "Shanghai" ], "origin": "Founded by a team of PhDs from multiple universities; reviewed materials do not specify a single founding university lab.", "funders": [], "website": "https://www.reexen.com/", "msources": [ "https://reexen.cn/gywm", "https://www.reexen.com/" ], "note": "Large-capacity ADA400 platform and early ADA series have different deployment/maturity stages.", "id": "reexen", "products": [ "reexen-ada100-ada200", "reexen-ada300n-ada300d-ada400-dn-board" ], "category": "Analog CIM" }, { "name": "Houmo AI", "native": "后摩智能", "city": [ "Beijing", "Nanjing", "Shanghai" ], "origin": "Founding team includes experienced AI chip researchers and industry engineers; a specific university lab spin-off has not been established.", "funders": [ "Lenovo Capital", "China Mobile investment arm", "Matrix Partners", "Qiming Venture Partners" ], "website": "https://www.houmo.cn/", "msources": [ "https://www.houmo.cn/AboutUs.html", "https://capital.lenovo.com/news/detail/id/606/s/1.html" ], "note": "The company describes Beijing as its nationwide headquarters since March 2026. Cities represent verified offices/headquarters where available, not all independently confirmed as fabrication R&D.", "id": "houmo-ai", "products": [ "houmo-ai-h30", "houmo-ai-m50", "houmo-ai-next-generation-3d-cim" ], "category": "Digital CIM" }, { "name": "Dongfang Suanxin", "native": "东方算芯", "city": [ "Shanghai", "Beijing", "Nanjing", "Xi'an", "Chengdu", "Suzhou", "Shenzhen" ], "origin": "Strong academic connection to Tsinghua University's software-defined/reconfigurable computing research led by Prof. Shaojun Wei; do not imply a formal corporate university spin-off without additional evidence.", "funders": [ "Xiaomi-related investment", "Meituan-related investment", "JD.com-related investment", "Hillhouse-related investment" ], "website": "https://www.dfsx.com/", "msources": [ "https://www.dfsx.com/", "https://www.semi.org.cn/site/semi/article/1727d0573fdd451b962e0f5f1721b220.html", "https://m.ithome.com/html/976025.htm" ], "note": "DF1000 is 3D stacked NMC; 6.4 TB/s is a vendor-reported figure whose measurement scope should be verified.", "id": "dongfang-suanxin", "products": [ "dongfang-suanxin-df1000-qy100-ty64" ], "category": "3D / near-memory" }, { "name": "PIMCHIP", "native": "苹芯科技", "city": [ "Beijing", "Shanghai", "Chengdu" ], "origin": "Research-led founding team spanning Duke University ECE (Yiran Chen and former doctoral student Yaojun Zhang) and industry IC design. The ISSCC 2022 28 nm, 32 Kb ADC-less digital SRAM-CIM macro was a formal collaboration with Peking University's Huang Ru–Bonan Yan group (School of Integrated Circuits / Institute for Artificial Intelligence), Duke University, NeoNexus and PIMCHIP. Bonan Yan earned his Duke PhD under Yiran Chen and Hai Li. Academic collaboration is documented; formal university spin-off status is not established.", "funders": [ "Primavera Venture Partners (春华创投)", "Redpoint China (红点中国)", "Sequoia China (红杉中国)", "ZhenFund (真格基金)" ], "website": "https://www.pimchip.cn/", "msources": [ "https://www.ai.pku.edu.cn/info/1053/2118.htm", "https://www.ai.pku.edu.cn/info/1137/1724.htm", "https://www.pimchip.cn/list/9.html", "https://tech.ifeng.com/c/8IEn7ui3jKV", "https://www.ithome.com/0/572/105.htm", "https://cei.pratt.duke.edu/people/yiran-chen", "https://ir.pku.edu.cn/handle/20.500.11897/665578", "https://www.isscc.org/s/ISSCC2022PressKit.pdf", "https://pitchhub.36kr.com/project/1679727635550979" ], "note": "The 2022 ISSCC result is a 32 Kb, 28 nm dynamic-logic-based ADC-less SRAM-CIM research macro (27.38 TOPS/W signed INT8; 1.041 Mb/mm² memory density), not an end-to-end S300 chip benchmark. Company website currently lists Beijing, Shanghai and Chengdu; older 36Kr profiles also report Hsinchu and Singapore offices, with current status unverified. Founder titles reflect their historically reported roles, not necessarily today's management.", "id": "pimchip", "products": [ "pimchip-pimchip-s300", "pimchip-pimchip-n300" ], "category": "Digital CIM", "people": [ { "name": "Yiran Chen · 陈怡然", "role": "Co-founder and founding chairman (reported 2021–2022); Duke ECE professor; ISSCC 2022 coauthor" }, { "name": "Yue Yang · 杨越", "role": "Co-founder and CEO (reported 2021–2026); former Micron system architect; ISSCC 2022 coauthor" }, { "name": "Yaojun Zhang · 章尧君", "role": "Co-founder and founding CTO (reported 2021–2022); former Duke founder's doctoral student at Pittsburgh; ISSCC 2022 coauthor" }, { "name": "Jeng-Long Hsu · 许振隆", "role": "Founding IC-design team member; former TSMC; ISSCC 2022 coauthor" }, { "name": "Bonan Yan · 燕博南", "role": "ISSCC 2022 first author; PKU research leader; Duke PhD supervised by Yiran Chen and Hai Li" }, { "name": "Ru Huang · 黄如", "role": "PKU research-group leader and ISSCC 2022 coauthor" } ] }, { "name": "InnoMemTech", "native": "新忆科技", "city": [ "Beijing" ], "origin": "Technology and founding team originated in the School of Integrated Circuits, Tsinghua University; the company explicitly identifies this origin.", "funders": [], "website": "https://www.innomemtech.com/", "msources": [ "https://www.innomemtech.com/about" ], "note": "30M+ shipped units refers to standalone RRAM memory products, not 30M CIM AI accelerators.", "id": "innomemtech", "products": [ "innomemtech-rram-ai-chips-embedded-ip" ], "category": "Memory enabler" }, { "name": "HSC Semiconductor", "native": "恒烁股份", "city": [ "Hefei" ], "origin": "No university lab spin-off established in reviewed sources.", "funders": [], "website": "https://www.hs-semi.com/", "msources": [], "note": "CiNOR availability and array-level details should be checked directly against HSC publications.", "id": "hsc-semiconductor", "products": [ "hsc-semiconductor-cinor-flash-cim" ], "category": "Analog CIM" }, { "name": "d-Matrix", "native": "", "city": [ "Santa Clara", "Bengaluru", "Sydney", "Toronto", "Belgrade" ], "origin": "Industry-founded by Sid Sheth and Sudeep Bhoja; no university spin-off identified.", "funders": [ "M12 (Microsoft)", "SK hynix", "Marvell", "Temasek", "Playground Global" ], "website": "https://www.d-matrix.ai/", "msources": [ "https://www.d-matrix.ai/announcements/d-matrix-announces-110-million-in-series-b-funding-to-make-generative-ai-commercially-viable-with-first-of-its-kind-inference-compute-platform/", "https://www.d-matrix.ai/announcements/d-matrix-raises-275-million-to-power-the-age-of-ai-inference/" ], "note": "Offices are cited, but the source does not explicitly characterize every office as a hardware R&D site.", "id": "d-matrix", "products": [ "d-matrix-corsair", "d-matrix-raptor-3d-dram" ], "category": "Digital CIM" }, { "name": "Axelera AI", "native": "", "city": [ "Eindhoven", "Leuven", "Zurich", "Milan", "Bristol" ], "origin": "Industrial incubation by Bitfury AI with imec involvement; researchers previously worked at IBM, imec and other labs. Not classified as a university spin-off.", "funders": [ "Samsung Catalyst Fund", "imec.xpand", "Innovation Industries", "Bitfury", "CDP Venture Capital" ], "website": "https://axelera.ai/", "msources": [ "https://axelera.ai/our-story", "https://axelera.ai/news/european-ai-startup-axelera-ai-closes-27-million-series-a", "https://axelera.ai/news/axelera-ai-secures-more-than-250-million-funding-on-global-commercial-growth" ], "note": "Europa figures are from a separate generation to Metis. Do not infer shipping from product-announcement specifications alone.", "id": "axelera-ai", "products": [ "axelera-ai-metis", "axelera-ai-europa" ], "category": "Digital CIM" }, { "name": "EnCharge AI", "native": "", "city": [ "Princeton", "Santa Clara" ], "origin": "Research spin-out from Prof. Naveen Verma’s electrical engineering group at Princeton University; underpinning work was conducted over several years.", "funders": [ "Samsung Ventures", "Tiger Global", "RTX Ventures", "Anzu Partners" ], "website": "https://www.enchargeai.com/", "msources": [ "https://www.enchargeai.com/about-us", "https://innovation.princeton.edu/about/annual-report" ], "note": "Charge-domain analog CIM. EN100 metrics are vendor claims; system precision and ADC treatment merit independent validation.", "id": "encharge-ai", "products": [ "encharge-ai-en100-m-2-4-chip-pcie" ], "category": "Analog CIM" }, { "name": "TetraMem", "native": "", "city": [ "Silicon Valley", "Singapore" ], "origin": "Co-founded by RRAM researchers including Miao Hu, Joshua Yang and Qiangfei Xia. No single official university spin-out claim established.", "funders": [], "website": "https://tetramem.com/", "msources": [ "https://tetramem.com/about-tetramem/", "https://tetramem.com/contact-us/" ], "note": "MLX200 status should be compared using production/sample distinctions supplied by the company.", "id": "tetramem", "products": [ "tetramem-mlx200" ], "category": "Analog CIM" }, { "name": "Mythic", "native": "", "city": [ "Austin", "Palo Alto" ], "origin": "Founded by semiconductor and analog-architecture researchers; no specific verified university-lab spin-off classification.", "funders": [ "Honda Motor", "Lockheed Martin", "S3 Ventures", "DCVC" ], "website": "https://www.mythic.ai/", "msources": [ "https://www.s3vc.com/mythic" ], "note": "M1076 is an established architecture; Vanguard is a next-generation roadmap rather than an equivalent shipping SKU.", "id": "mythic", "products": [ "mythic-m1076-amp", "mythic-vanguard" ], "category": "Analog CIM" }, { "name": "UPMEM", "native": "", "city": [ "Grenoble", "Paris" ], "origin": "Industrial/founding research history in memory processing; a specific formal university spin-off could not be established from sources reviewed.", "funders": [], "website": "https://www.upmem.com/", "msources": [ "https://www.upmem.com/" ], "note": "Processing occurs in DRAM chips, not by storing fixed neural weights in analog crossbar cells.", "id": "upmem", "products": [ "upmem-dram-pim-ddr4-dimm" ], "category": "DRAM PIM" }, { "name": "SK hynix", "native": "SK하이닉스", "city": [ "Icheon", "Bundang / Seongnam" ], "origin": "Established integrated memory manufacturer; not a university spin-off.", "funders": [], "website": "https://www.skhynix.com/", "msources": [ "https://news.skhynix.com/" ], "note": "AiM demo material should not be conflated with the company’s standard commercial GDDR products.", "id": "sk-hynix", "products": [ "sk-hynix-gddr6-aim-aimx" ], "category": "DRAM PIM" }, { "name": "Samsung Electronics", "native": "삼성전자", "city": [ "Suwon", "Hwaseong" ], "origin": "Established semiconductor manufacturer; not a university spin-off.", "funders": [], "website": "https://semiconductor.samsung.com/", "msources": [ "https://semiconductor.samsung.com/" ], "note": "PIM demonstrations are separate from standard commercial DRAM and HBM production.", "id": "samsung-electronics", "products": [ "samsung-electronics-hbm2-pim-aquabolt-xl", "samsung-electronics-lpddr5x-pim-2026-demo" ], "category": "DRAM PIM" }, { "name": "GSI Technology", "native": "", "city": [ "Sunnyvale" ], "origin": "Established SRAM manufacturer; not a university spin-off.", "funders": [], "website": "https://www.gsitechnology.com/", "msources": [ "https://www.gsitechnology.com/" ], "note": "Associative/Boolean POPS cannot be converted directly to dense GEMM TOPS.", "id": "gsi-technology", "products": [ "gsi-technology-gemini-i-gemini-ii-apu" ], "category": "Associative / NMC" }, { "name": "NeuroBlade", "native": "", "city": [ "Tel Aviv", "Palo Alto" ], "origin": "Industry-founded data-processing company; university spin-off not verified.", "funders": [], "website": "https://neuroblade.com/", "msources": [ "https://neuroblade.com/" ], "note": "Specialized analytical query execution near data, not tensor MAC CIM.", "id": "neuroblade", "products": [ "neuroblade-spu-daxl" ], "category": "Associative / NMC" }, { "name": "Synthara", "native": "", "city": [ "Zurich" ], "origin": "Formal University of Zurich / ETH Zurich spin-off from the Institute of Neuroinformatics, founded by Manu V. Nair and Alessandro Aimar.", "funders": [ "High-Tech Gründerfonds", "Zürcher Kantonalbank", "DeepIE" ], "website": "https://synthara.ai/", "msources": [ "https://www.innovation.uzh.ch/en/stories/news/2024/27.6.2024_Synthara_financing-.html" ], "note": "ComputeRAM is embedded macro IP—not a standalone board or accelerator.", "id": "synthara", "products": [ "synthara-computeram-ip" ], "category": "Digital CIM" } ], "products": [ { "id": "yizhu-technology-3d-dram-digital-cim-family-yica", "companyId": "yizhu-technology", "name": "3D-DRAM digital CIM family / YICA", "companyName": "Yizhu Technology", "native": "亿铸科技", "class": "Digital CIM + 3D-memory hybrid", "category": "3D / near-memory", "locus": "CIM + vertically integrated DRAM", "memory": "3D DRAM; earlier RRAM work", "mode": "Digital", "precision": "Mixed precision; bit widths ND", "array": "Not publicly disclosed", "system": "Card / workstation / inference cluster marketed; exact capacity ND", "node": "Not publicly disclosed", "throughput": "Claimed 32 TB/s effective bandwidth (architecture figure; verify basis)", "power": "Not publicly disclosed", "coprocessor": "RISC-V/vector/heterogeneous digital control", "scale": "PCIe / RoCE / RDMA; YZCCL cluster software", "software": "YICA ISA, CUDA-compatible compiler, PyTorch/Triton integration", "maturity": "Taped out; company says full-chain validated; volume status unclear", "stage": "Validation / sampling", "confidence": "Primary vendor; mixed verification", "caveat": "Important technology update: official 2026 site calls its core 3D DRAM; older articles label it RRAM. 88% TCO reduction vendor claim not independent benchmark.", "sources": [ "https://www.yizhu-tech.com/about.php", "https://www.yizhu-tech.com/newsv.php?id=124" ] }, { "id": "memsilicon-mounttai-2026", "companyId": "memsilicon", "name": "MountTai 2026 (泰山一号)", "companyName": "MemSilicon", "native": "铭芯启睿", "class": "Enabling memory technology; hybrid CIM roadmap", "category": "Memory enabler", "locus": "RRAM standalone storage (not computing array)", "memory": "RRAM 1T4R", "mode": "Digital memory device; compute mode not specified", "precision": "Not publicly disclosed", "array": "1 Gb is storage-array capacity, NOT MAC-array capacity", "system": "1 Gb RRAM single die", "node": "28 nm", "throughput": "<20 ns access; density 30 Mb/mm²", "power": "Not publicly disclosed", "coprocessor": "On-die ECC", "scale": "No compute board/product demonstrated", "software": "RRAM IP; RRAM+DRAM hybrid CIM roadmap", "maturity": "Taped out 14 Oct 2026; undergoing verification", "stage": "Validation / sampling", "confidence": "High for memory specs; no CIM product proof", "caveat": "Do not put 1 Gb into a compute-in-memory accelerator comparison as if RRAM MAC were validated.", "sources": [ "https://memsilicon.com/newsinfo/11354864.html", "https://memsilicon.com/gsjj" ] }, { "id": "micronanocore-3d-cim-pcie-cim-lp-cim", "companyId": "micronanocore", "name": "3D-CIM; PCIe-CIM; LP-CIM", "companyName": "MicroNanoCore", "native": "微纳核芯", "class": "3D hybrid CIM", "category": "3D / near-memory", "locus": "SRAM matrix engine coupled to vertically stacked memory", "memory": "SRAM CIM + DRAM/NAND stack", "mode": "Digital / mixed mode not fully disclosed", "precision": "Not publicly disclosed", "array": "Not publicly disclosed", "system": "3D-CIM hierarchy; quant capacity ND", "node": "Not publicly disclosed", "throughput": "Not publicly disclosed", "power": "Not publicly disclosed", "coprocessor": "RISC-V compute/control", "scale": "PCIe card and LP-CIM plans", "software": "RV-CIM ISA; compiler; function libraries; simulator", "maturity": "Product/architecture announced; 2026 tapeout roadmap; shipment unverified", "stage": "Roadmap", "confidence": "Medium; company publicity", "caveat": "Volume claims from unrelated legacy chips cannot be credited to 3D-CIM products.", "sources": [ "https://www.nanocorechip.com/", "https://www.thepaper.cn/newsDetail_forward_32918058" ] }, { "id": "witmem-wtm2101", "companyId": "witmem", "name": "WTM2101", "companyName": "WITMEM", "native": "知存科技", "class": "Analog Flash CIM", "category": "Analog CIM", "locus": "Analog matrix/NN computation inside flash memory", "memory": "Embedded NOR Flash", "mode": "Analog IMC with digital supervision", "precision": "INT8 inference reported", "array": "~1.8 million stored model parameters (vendor max)", "system": "On-chip nonvolatile weights, not HBM/DRAM", "node": "Not publicly disclosed", "throughput": "50 GOPS (INT8)", "power": "5 μA–3 mA reported operating range", "coprocessor": "RISC-V/microcontroller + audio front end", "scale": "Standalone edge SoC; no multi-chip scale-up", "software": "WTM SDK / model tools; developer resources", "maturity": "Mass-production/fielded edge product (vendor)", "stage": "Production", "confidence": "Primary vendor", "caveat": "Do not compare 50 GOPS with TOPS without unit normalization; flash analog array not equal whole MCU memory.", "sources": [ "https://www.witmem.com/", "https://www.witmem.com/WTM-8.php" ] }, { "id": "witmem-wtm-8", "companyId": "witmem", "name": "WTM-8", "companyName": "WITMEM", "native": "知存科技", "class": "3D hybrid CIM for vision", "category": "Analog CIM", "locus": "4 compute cores plus 3D memory architecture", "memory": "Flash-derived proprietary 3D CIM; exact array medium ND", "mode": "Mixed-signal; exact implementation ND", "precision": "8-bit", "array": "Vendor advertises 64M per core; unit/definition ambiguous", "system": "System memory capacity ND", "node": "Mature process (exact nm ND)", "throughput": ">24 TOPS", "power": "<3 W headline (other application numbers differ)", "coprocessor": "Image/vision processing / Linux", "scale": "Chip-based edge appliance; multi-chip ND", "software": "Linux, WITMEM SDK + model ecosystem", "maturity": "Published product pages; coming-soon/early production status needs confirmation", "stage": "Roadmap", "confidence": "Primary vendor", "caveat": "Do not silently convert 64M into MB or number of parameters; vendor did not state unit.", "sources": [ "https://www.witmem.com/WTM-8.php", "https://www.witmem.com/" ] }, { "id": "reexen-ada100-ada200", "companyId": "reexen", "name": "ADA100 / ADA200", "companyName": "REEXEN", "native": "九天睿芯", "class": "Analog/mixed-signal SRAM CIM + sensing", "category": "Analog CIM", "locus": "SRAM array mixed-signal multiply + ASP sensor preprocessing", "memory": "6T SRAM / local analog sensor circuitry", "mode": "Mixed analog/digital", "precision": "INT8 class; exact conversion details ND", "array": "Not publicly disclosed", "system": "On-chip capacity ND", "node": "ADA100 55 nm reported", "throughput": "Application-dependent, public specs heterogeneous", "power": "Sub-mW ASP operating points claimed (not whole chip)", "coprocessor": "Sensor ASP + control logic", "scale": "Standalone edge/AIoT", "software": "Proprietary mapping / vendor support", "maturity": "Older released/sampled edge devices; product shipments claimed", "stage": "Validation / sampling", "confidence": "Medium vendor + media", "caveat": "Differentiate always-on sensing power from neural engine peak power.", "sources": [ "https://www.reexen.com/", "https://www.thepaper.cn/newsDetail_forward_32918058" ] }, { "id": "reexen-ada300n-ada300d-ada400-dn-board", "companyId": "reexen", "name": "ADA300N / ADA300D / ADA400-DN-Board", "companyName": "REEXEN", "native": "九天睿芯", "class": "SRAM CIM + 3D NAND/DRAM NMC", "category": "Analog CIM", "locus": "SRAM in-array MAC + vertical NAND/DRAM + attention", "memory": "SRAM, NAND, DRAM, HBF SSD", "mode": "Mixed analog/digital CIM + digital hybrid", "precision": "Not publicly disclosed", "array": "SRAM-CIM macro not disclosed", "system": "ADA400-DN-Board marketed at >2 TB (whole BOARD storage)", "node": "Chip process ND", "throughput": "ADA400-DN-Board >4 TB/s marketed (level ND)", "power": "ND", "coprocessor": "Heterogeneous Attention processor / NPU", "scale": "Chiplets; vertical bonding; larger AI server", "software": "MPM (memory-processor-model) software co-design", "maturity": "New platform/roadmap; no independent volume proof", "stage": "Roadmap", "confidence": "Vendor roadmap; medium for plans", "caveat": "2 TB+ must not be presented as compute SRAM array. Claimed 4 TB/s not automatically external PCIe BW.", "sources": [ "https://www.reexen.com/", "https://www.reexen.com/" ] }, { "id": "houmo-ai-h30", "companyId": "houmo-ai", "name": "H30 (鸿途)", "companyName": "Houmo AI", "native": "后摩智能", "class": "Digital SRAM-CIM AI SoC", "category": "Digital CIM", "locus": "Digital bit-serial / SRAM bank compute", "memory": "SRAM CIM", "mode": "Digital", "precision": "INT8", "array": "ND", "system": "External storage subsystem ND", "node": "12 nm reported", "throughput": "256 TOPS INT8", "power": "35 W SoC stated", "coprocessor": "IPU + SoC processors", "scale": "Automotive application; inter-chip ND", "software": "后摩大道 / model compiler / deployment", "maturity": "Released commercial automotive/edge product (supplier claim)", "stage": "Available / claimed", "confidence": "Vendor + industry", "caveat": "Marketing TOPS/W across chip vs array differs.", "sources": [ "https://www.houmoai.com/", "https://www.thepaper.cn/newsDetail_forward_32918058" ] }, { "id": "houmo-ai-m50", "companyId": "houmo-ai", "name": "M50 (漫界)", "companyName": "Houmo AI", "native": "后摩智能", "class": "Digital SRAM-CIM", "category": "Digital CIM", "locus": "Dual-port SRAM-CIM array + digital IPU", "memory": "SRAM-CIM with external LPDDR5", "mode": "Digital CIM", "precision": "INT8, INT16, FP16, FP32, bFP16, bFP24 supported", "array": "On-array SRAM size ND", "system": "Up to 48 GB LPDDR5; up to 153.6 GB/s external BW", "node": "Not publicly disclosed", "throughput": "160 TOPS INT8; 100 TFLOPS bFP16", "power": "10 W typical chip", "coprocessor": "2nd gen Tianxuan IPU; low-power MCU", "scale": "PCIe Gen4 x4; HM-Link 16 GB/s; multi-die cards", "software": "Houmo Dadao stack; model conversion / runtime", "maturity": "Company-reported commercial volume in 2025/26", "stage": "Available / claimed", "confidence": "High primary source for announced specs", "caveat": "48 GB is LPDDR5 capacity, not SRAM-CIM array; power excludes whole system/card unless stated.", "sources": [ "https://www.houmoai.com/60/ProductType.html", "https://www.houmoai.com/1/35/NewsDetails.html" ] }, { "id": "houmo-ai-next-generation-3d-cim", "companyId": "houmo-ai", "name": "Next-generation 3D CIM", "companyName": "Houmo AI", "native": "后摩智能", "class": "Hybrid 3D CIM roadmap", "category": "Digital CIM", "locus": "SRAM-CIM with vertically integrated memory", "memory": "SRAM + 3D DRAM", "mode": "Digital + 3D NMC", "precision": "Not publicly disclosed", "array": "Not publicly disclosed", "system": "Not publicly disclosed", "node": "Not publicly disclosed", "throughput": "Claims 2× compute in equivalent area", "power": "Not publicly disclosed", "coprocessor": "IPU + memory-tier circuitry", "scale": "Vertical integration / future products", "software": "Existing Houmo software stack", "maturity": "Architecture roadmap; not shipping silicon", "stage": "Roadmap", "confidence": "Vendor announcement", "caveat": "Do not attribute this 3D architecture to currently shipping M50.", "sources": [ "https://www.houmo.cn/Technology.html", "https://www.ithome.com/1/005/988.htm" ] }, { "id": "dongfang-suanxin-df1000-qy100-ty64", "companyId": "dongfang-suanxin", "name": "DF1000 / QY100 / TY64", "companyName": "Dongfang Suanxin", "native": "东方算芯", "class": "3D stacked near-memory computing", "category": "3D / near-memory", "locus": "3D hybrid-bonded DRAM + logic processing tier", "memory": "3D DRAM", "mode": "Digital NMC; in-array MAC not evidenced", "precision": "Not publicly disclosed", "array": "Not publicly disclosed", "system": "DF1000 / TY64 products; per-chip capacity ND", "node": "Not publicly disclosed", "throughput": "Claimed 6.4 TB/s single-chip memory bandwidth", "power": "Not publicly disclosed", "coprocessor": "Logic die / software-defined accelerators", "scale": "DF1000 cards, QY100 servers, TY64 64-card server", "software": "Software-defined runtime (compiler names ND)", "maturity": "DF1000 announced July 2026; independent volume status ND", "stage": "Announced", "confidence": "Secondary release-based", "caveat": "6.4 TB/s is vendor-internal memory BW claim, not external bandwidth.", "sources": [ "https://www.trendforce.cn/industry-news/semiconductors/20260714-6437.html", "https://www.thepaper.cn/newsDetail_forward_32918058" ] }, { "id": "pimchip-pimchip-s300", "companyId": "pimchip", "name": "PIMCHIP-S300", "companyName": "PIMCHIP", "native": "苹芯科技", "class": "SRAM CIM SoC", "category": "Digital CIM", "locus": "SRAM in-array accelerator plus NPU", "memory": "SRAM-CIM; system SRAM; PSRAM", "mode": "Digital/mixed CIM (circuit details ND)", "precision": "INT4 / INT8 / INT16", "array": "Macro CIM capacity ND", "system": "Up to 1,792 KB system SRAM; up to 32 MB PSRAM", "node": "28 nm reported for family", "throughput": "0.5 TOPS NPU; 100 GMAC DSP", "power": "100 μW–5 mW is AON subsystem only", "coprocessor": "300 DMIPS MCU, DSP, image subsystems", "scale": "Embedded SoC; no explicit scale-up", "software": "RTOS, middleware, model zoo, one-click deployment", "maturity": "Published product", "stage": "Announced", "confidence": "High primary", "caveat": "DO NOT interpret AON subsystem power as 0.5-TOPS operating power.", "sources": [ "https://pimchip.cn/list/4.html", "https://www.pimchip.cn/" ] }, { "id": "innomemtech-rram-ai-chips-embedded-ip", "companyId": "innomemtech", "name": "RRAM AI chips / embedded IP", "companyName": "InnoMemTech", "native": "新忆科技", "class": "RRAM CIM + memory IP", "category": "Memory enabler", "locus": "RRAM analog/heterogeneous compute claimed; memory IP distinct", "memory": "RRAM, embedded and standalone", "mode": "RRAM-CIM approach (compute implementation ND)", "precision": "ND", "array": "Not publicly disclosed", "system": "Standalone memory capacities ND", "node": "ND", "throughput": "ND", "power": "ND", "coprocessor": "Hybrid accelerator & memory products", "scale": "Edge/cloud product portfolio stated", "software": "ND", "maturity": "Standalone RRAM memory in production since 2021; AI CIM SoC status separate", "stage": "Not independently established", "confidence": "High company; limited chip specs", "caveat": "Vendor says >30M standalone RRAM memory chips shipped—not proof of 30M CIM accelerator shipments.", "sources": [ "https://www.innomemtech.com/", "https://www.innomemtech.com/about" ] }, { "id": "hsc-semiconductor-cinor-flash-cim", "companyId": "hsc-semiconductor", "name": "CiNOR (Flash CIM)", "companyName": "HSC Semiconductor", "native": "恒烁股份", "class": "Embedded NOR-Flash analog CIM", "category": "Analog CIM", "locus": "NOR Flash array / peripheral CIM", "memory": "NOR Flash (ETOX class)", "mode": "Analog CIM expected; details ND", "precision": "Not publicly disclosed", "array": "Not publicly disclosed", "system": "Not publicly disclosed", "node": "65 nm Flash cited historically", "throughput": "Not publicly disclosed", "power": "Not publicly disclosed", "coprocessor": "Edge microcontroller interfaces", "scale": "Not publicly disclosed", "software": "Not publicly disclosed", "maturity": "Prototype / technology activity; product detail limited", "stage": "Not independently established", "confidence": "Medium secondary", "caveat": "Memory production alone should not be conflated with proven CIM accelerator shipment.", "sources": [ "https://www.eefocus.com/article/2014340.html", "https://pdf.dfcfw.com/pdf/H3_AP202501061641827585_1.pdf" ] }, { "id": "d-matrix-corsair", "companyId": "d-matrix", "name": "Corsair", "companyName": "d-Matrix", "native": "", "class": "Digital SRAM IMC (datacenter)", "category": "Digital CIM", "locus": "Digital compute tightly integrated with SRAM", "memory": "2 GB on-card compute SRAM + off-card LPDDR5", "mode": "Digital", "precision": "MXINT8 / MXINT4 / MX formats", "array": "2 GB of integrated Performance Memory per card (aggregate; not one macro)", "system": "Up to 256 GB LPDDR5 capacity memory / card", "node": "TSMC N6", "throughput": "2,400 TFLOPS MXINT8; 9,600 TFLOPS MXINT4; 150 TB/s local SRAM BW", "power": "Card/system power not given consistently", "coprocessor": "Digital MAC, control and vector operators", "scale": "PCIe Gen5, DMX Link/Bridge; multi-card racks", "software": "Aviator compiler/runtime; GPU co-processing support", "maturity": "Full production announced June 2026; volume shipment beginning", "stage": "Production", "confidence": "High primary specs; availability is vendor claim", "caveat": "2 GB is distributed compute SRAM on a card; 256 GB LPDDR is capacity memory. Peak TFLOPS not measured LLM goodput.", "sources": [ "https://www.d-matrix.ai/announcements/d-matrix-unveils-corsair-the-worlds-most-efficient-ai-computing-platform-for-inference-in-datacenters/", "https://www.d-matrix.ai/announcements/d-matrix-corsair-ai-inference-platform-enters-full-production-to-meet-customer-demand/" ] }, { "id": "d-matrix-raptor-3d-dram", "companyId": "d-matrix", "name": "Raptor 3D DRAM", "companyName": "d-Matrix", "native": "", "class": "Digital 3D DIMC roadmap", "category": "Digital CIM", "locus": "Compute die integrated under/adjacent 3D DRAM", "memory": "3D DRAM + SRAM tiers", "mode": "Digital", "precision": "Not publicly disclosed", "array": "Not publicly disclosed", "system": "Not publicly disclosed", "node": "Not publicly disclosed", "throughput": "Not publicly disclosed", "power": "Not publicly disclosed", "coprocessor": "Digital inference accelerator", "scale": "Expected 3D memory scaling", "software": "Aviator ecosystem likely; not a supported SKU", "maturity": "Roadmap / concept", "stage": "Roadmap", "confidence": "Company roadmap", "caveat": "Do not confuse next-gen Raptor concept with Corsair shipping memory hierarchy.", "sources": [ "https://www.d-matrix.ai/", "https://www.d-matrix.ai/announcements/d-matrix-corsair-ai-inference-platform-enters-full-production-to-meet-customer-demand/" ] }, { "id": "axelera-ai-metis", "companyId": "axelera-ai", "name": "Metis", "companyName": "Axelera AI", "native": "", "class": "Digital SRAM CIM", "category": "Digital CIM", "locus": "True in-SRAM-array MVM across 4 AI cores", "memory": "SRAM-CIM + DDR", "mode": "Digital", "precision": "INT8 weights/activations", "array": "Core-level CIM array size ND", "system": "4 GB DDR per typical board", "node": "ND", "throughput": "~214 TOPS INT8 per AIPU", "power": "Board-dependent; core power claims not whole system", "coprocessor": "4 IMC cores + host CPU for prep/post", "scale": "PCIe Gen3 x4; multiple AIPUs per board", "software": "Voyager SDK, compiler, model zoo, ONNX / Python", "maturity": "Commercial M.2 / PCIe / compute boards", "stage": "Available / claimed", "confidence": "High vendor docs", "caveat": "Vendor documentation uses ambiguous TOPS/MAC wording: align MAC convention before comparative ranking.", "sources": [ "https://docs.axelera.ai/sdk/reference/system/hardware/", "https://axelera.ai/ai-accelerators" ] }, { "id": "axelera-ai-europa", "companyId": "axelera-ai", "name": "Europa", "companyName": "Axelera AI", "native": "", "class": "Digital SRAM CIM (next generation)", "category": "Digital CIM", "locus": "More in-SRAM compute cores with RISC-V vector processors", "memory": "SRAM-CIM + up to 64 GB backing memory", "mode": "Digital", "precision": "INT4 / INT8 / INT16", "array": "128 MB L2 SRAM; 8 IMC cores (macro breakdown ND)", "system": "Up to 64 GB module memory; 200 GB/s DRAM bandwidth", "node": "ND", "throughput": "629 TOPS INT8 marketed", "power": "~45 W cited in product promotion", "coprocessor": "16 RISC-V vector cores", "scale": "Multi-chip support for larger models claimed", "software": "Voyager SDK next-generation stack", "maturity": "Next-generation product / announced; volume unverified", "stage": "Announced", "confidence": "High vendor roadmap", "caveat": "Do not represent as currently shipping in the same way as Metis.", "sources": [ "https://axelera.ai/ai-accelerators", "https://docs.axelera.ai/sdk/reference/system/hardware/" ] }, { "id": "encharge-ai-en100-m-2-4-chip-pcie", "companyId": "encharge-ai", "name": "EN100 M.2 / 4-chip PCIe", "companyName": "EnCharge AI", "native": "", "class": "Charge-domain analog CIM", "category": "Analog CIM", "locus": "Charge-domain analog MAC on capacitor-SRAM-like arrays", "memory": "CMOS metal capacitors / SRAM-associated data", "mode": "Analog with digital precision fallback", "precision": "INT8 peak; other precision digital path ND", "array": "Analog macro sizes ND", "system": "M.2 32 GB LPDDR; 4-chip PCIe 128 GB", "node": "16 nm reported", "throughput": ">200 TOPS M.2; up to ~1 POPS 4-chip PCIe", "power": "8.25 W M.2; ~40 W PCIe announced", "coprocessor": "On-chip RISC-V plus digital compute", "scale": "M.2, PCIe; 4 chips on card", "software": "Proprietary SDK; model partnerships", "maturity": "Announced; early access/sampling; independent benchmarks limited", "stage": "Validation / sampling", "confidence": "Company figures via specialist press", "caveat": "Do not divide 200 TOPS by 8.25 W and call it directly comparable to peak 40 TOPS/W: envelope vs core efficiency differ.", "sources": [ "https://www.enchargeai.com/technology", "https://www.eetimes.com/encharge-picks-the-pc-for-its-first-analog-ai-chip/" ] }, { "id": "tetramem-mlx200", "companyId": "tetramem", "name": "MLX200", "companyName": "TetraMem", "native": "", "class": "Analog RRAM CIM", "category": "Analog CIM", "locus": "RRAM crossbar analog VMM", "memory": "Multi-level RRAM crossbars", "mode": "Analog mixed-signal", "precision": "ONNX compiler INT8 / INT4; physical 8-bit multilevel claims", "array": "4M 8-bit weights (company showcase)", "system": "On-array nonvolatile weights; external memory ND", "node": "TSMC 22 nm", "throughput": "~0.5 TOPS marketed", "power": "<1 W company target/showcase", "coprocessor": "RISC-V / digital orchestration", "scale": "Small edge SoC", "software": "ONNX compile + quantization, C++ and RISC-V", "maturity": "Silicon validation May 2026; eval kits expected H2 2026", "stage": "Validation / sampling", "confidence": "High primary for stage and specs", "caveat": "2026 production shipments shown on roadmap; independently confirmed volume not found.", "sources": [ "https://tetramem.com/tetramem-completes-mlx200-silicon-validation/", "https://tetramem.dev/" ] }, { "id": "mythic-m1076-amp", "companyId": "mythic", "name": "M1076 AMP", "companyName": "Mythic", "native": "", "class": "Analog Flash CIM", "category": "Analog CIM", "locus": "Analog Flash-array matrix MAC", "memory": "Embedded Flash", "mode": "Analog with digital/CPU", "precision": "INT8-class, analog weight representation", "array": "Up to ~80M weights company brochure", "system": "Weight storage on-chip", "node": "ND", "throughput": "~25 TOPS marketed", "power": "~3–4 W reported for chip", "coprocessor": "76 Analog Compute Tiles; RISC-V microcontrollers", "scale": "PCIe accelerator variants", "software": "Mythic compiler/toolchain", "maturity": "Earlier shipped/sampled generation; current market availability uncertain", "stage": "Validation / sampling", "confidence": "Historical company spec", "caveat": "Performance applies to M1076 generation; do not mix with planned Vanguard.", "sources": [ "https://mythic.ai/", "https://www.mythic.ai/" ] }, { "id": "mythic-vanguard", "companyId": "mythic", "name": "Vanguard", "companyName": "Mythic", "native": "", "class": "Analog Flash + digital companion", "category": "Analog CIM", "locus": "Flash analog IMC die and digital die / hybrid", "memory": "SuperFlash + digital memory", "mode": "Analog/digital", "precision": "ND", "array": "ND", "system": "ND", "node": "ND", "throughput": "Next-gen >100 TOPS/W target claims", "power": "ND", "coprocessor": "Companion digital accelerator", "scale": "3D/heterogeneous packaging roadmap", "software": "Mythic software stack", "maturity": "Future product advertised for 2027", "stage": "Not independently established", "confidence": "Roadmap", "caveat": "Do not count as 2026 shipping product.", "sources": [ "https://mythic.ai/", "https://www.mythic.ai/" ] }, { "id": "upmem-dram-pim-ddr4-dimm", "companyId": "upmem", "name": "DRAM-PIM DDR4 DIMM", "companyName": "UPMEM", "native": "", "class": "Programmable DRAM PIM", "category": "DRAM PIM", "locus": "Programmable processors alongside DRAM banks", "memory": "DDR4 DRAM", "mode": "Digital scalar RISC processing", "precision": "32-bit RISC (not native GEMM INT8 precision metric)", "array": "64 MB DRAM per DPU (memory portion)", "system": "128 DPUs/DIMM => 8 GB DRAM/DIMM", "node": "DRAM process proprietary", "throughput": "450 MHz / DPU; 2,560 DPUs in 20-DIMM examples", "power": "System dependent", "coprocessor": "24 threads/DPU; 64 KB WRAM + 24 KB IRAM", "scale": "Host-mediated inter-DPU; no direct DPU-to-DPU network", "software": "UPMEM C / Rust SDK, host APIs, compiler", "maturity": "Commercial dev and server deployments", "stage": "Available / claimed", "confidence": "High architectural documentation", "caveat": "2.56 TB/s aggregate local DPU bandwidth is not CPU/DIMM interface bandwidth; not a native tensor TOPS product.", "sources": [ "https://www.upmem.com/", "https://github.com/upmem" ] }, { "id": "sk-hynix-gddr6-aim-aimx", "companyId": "sk-hynix", "name": "GDDR6-AiM / AiMX", "companyName": "SK hynix", "native": "SK하이닉스", "class": "DRAM PIM (bank processing units)", "category": "DRAM PIM", "locus": "Digital vector processing near DRAM banks", "memory": "GDDR6 DRAM", "mode": "Digital", "precision": "BF16", "array": "32 PUs per 8 Gb chip", "system": "8 Gb per GDDR6-AiM chip", "node": "1y DRAM technology", "throughput": "1 TFLOPS BF16 per chip; 64 GB/s external chip BW", "power": "ND", "coprocessor": "AiM controller, CPU/GPU host, FPGA ref platform", "scale": "AiMX accelerator board; GPU co-processing demos", "software": "AiM software stack, PyTorch/ONNX experimental", "maturity": "Physical prototype / demonstration; no high-volume AiMX evidence", "stage": "Not independently established", "confidence": "High archival primary HotChips", "caveat": "8 Gb DRAM capacity is not processing array weights; PUs inserted alongside banks.", "sources": [ "https://hc34.hotchips.org/assets/program/posters/hc34.SKhynix.YongkeeKwon.v03.pdf", "https://news.skhynix.com/en/sk-hynix-debuts-first-gddr6-aim-accelerator-card-aimx-for-generative-ai/" ] }, { "id": "samsung-electronics-hbm2-pim-aquabolt-xl", "companyId": "samsung-electronics", "name": "HBM2-PIM / Aquabolt-XL", "companyName": "Samsung Electronics", "native": "삼성전자", "class": "HBM DRAM PIM", "category": "DRAM PIM", "locus": "Processing units in HBM DRAM bank-periphery", "memory": "HBM2 DRAM", "mode": "Digital PIM", "precision": "FP16-class operation (verify product generation)", "array": "HBM bank count SKU-dependent", "system": "HBM stack memory; exact SKU varies", "node": "HBM manufacturing process ND", "throughput": "Vendor benchmark workload-dependent", "power": "ND", "coprocessor": "Host processor + in-HBM processing", "scale": "GPU/CPU co-processing prototype", "software": "PIM programming/system software demos", "maturity": "Demonstrated prototype; mass-market PIM availability unclear", "stage": "Not independently established", "confidence": "Primary demonstrations", "caveat": "Do not conflate commercial HBM4 shipments with computing-enabled HBM-PIM.", "sources": [ "https://semiconductor.samsung.com/", "https://semiconductor.samsung.com/news-events/" ] }, { "id": "samsung-electronics-lpddr5x-pim-2026-demo", "companyId": "samsung-electronics", "name": "LPDDR5X-PIM (2026 demo)", "companyName": "Samsung Electronics", "native": "삼성전자", "class": "DRAM PIM", "category": "DRAM PIM", "locus": "Computing near LPDDR DRAM banks", "memory": "LPDDR5X DRAM", "mode": "Digital PIM (implementation details ND)", "precision": "ND", "array": "ND", "system": "LPDDR5X system memory density ND", "node": "Not publicly disclosed", "throughput": "Company reports up to 8× effective BW and 2–3× inference throughput in selected demos", "power": "ND", "coprocessor": "Host SoC / DRAM compute", "scale": "Mobile / system demos", "software": "Vendor prototype tools", "maturity": "2026 demo / precommercial", "stage": "Available / claimed", "confidence": "Primary Samsung announcements", "caveat": "Do not treat relative demo speedups as independent all-workload benchmarks.", "sources": [ "https://semiconductor.samsung.com/news-events/news/samsung-unveils-next-gen-3d-memory-vision-at-fms-2026-charting-the-future-of-ai-infrastructure/", "https://semiconductor.samsung.com/" ] }, { "id": "gsi-technology-gemini-i-gemini-ii-apu", "companyId": "gsi-technology", "name": "Gemini I / Gemini II APU", "companyName": "GSI Technology", "native": "", "class": "Digital SRAM associative IMC", "category": "Associative / NMC", "locus": "Boolean/associative processing inside SRAM arrays", "memory": "SRAM", "mode": "Digital Boolean associative", "precision": "Variable bit-level Boolean operations (not directly GEMM INT8)", "array": "In-memory associative array; capacity SKU-dependent", "system": "Leda-E / Leda-S cards and servers", "node": "ND", "throughput": "1U 16-card 15 POPS Boolean (not MAC TOPS)", "power": "Edge power SKU dependent", "coprocessor": "Host code + associative engine", "scale": "PCIe cards; 2U 8-card / 1U 16-card servers", "software": "APU SDK, custom APIs, libraries", "maturity": "Gemini I full production limited sales; Gemini II preproduction in 2026 SEC filing", "stage": "Production", "confidence": "Very high primary regulatory", "caveat": "Very important: Boolean POPS cannot be meaningfully compared with neural MAC TOPS; APU revenue immaterial per SEC filing.", "sources": [ "https://www.sec.gov/Archives/edgar/data/1126741/000110465926070962/gsit-20260331x10k.htm", "https://gsitechnology.com/hpc-overview/" ] }, { "id": "neuroblade-spu-daxl", "companyId": "neuroblade", "name": "SPU / DAXL", "companyName": "NeuroBlade", "native": "", "class": "Near-data analytics accelerator", "category": "Associative / NMC", "locus": "Compute engines close to memory for SQL/analytics", "memory": "DRAM-centric memory system (proprietary)", "mode": "Digital", "precision": "Data-analytics operators, not ML INT8 MAC", "array": "ND", "system": "Memory + PCIe cards system ND", "node": "Not publicly disclosed", "throughput": "Database query workload metrics, not NN TOPS", "power": "Not publicly disclosed", "coprocessor": "Dedicated analytics SPU", "scale": "Server acceleration", "software": "DAXL / Presto / Spark / ClickHouse integration", "maturity": "Commercial customer deployments claimed", "stage": "Available / claimed", "confidence": "Vendor-reported", "caveat": "Strong PNM use case for databases; not an LLM inference tensor engine.", "sources": [ "https://neuroblade.com/", "https://www.neuroblade.com/" ] }, { "id": "synthara-computeram-ip", "companyId": "synthara", "name": "ComputeRAM IP", "companyName": "Synthara", "native": "", "class": "Digital SRAM CIM macro IP", "category": "Digital CIM", "locus": "SRAM macro implements MVM operations", "memory": "Standard CMOS SRAM", "mode": "Digital bit-accurate", "precision": "Integer signed/unsigned; 8b MAC example", "array": "17 KB macro", "system": "Licensed embedded IP, NOT stand-alone accelerator", "node": "GlobalFoundries 22FDX", "throughput": "Performance application-dependent; no fixed TOPS public", "power": "System dependent", "coprocessor": "Host Arm/RISC-V/x86 MCU", "scale": "Embedded macro integration; no scale-up", "software": "SDK, optimized kernels; TFLite/PyTorch/ONNX; Renode", "maturity": "Available semiconductor IP / reference implementation", "stage": "Not independently established", "confidence": "High official datasheet", "caveat": "Macro kilobytes cannot be compared with card backing LPDDR gigabytes.", "sources": [ "https://synthara.ai/wp-content/uploads/2024/08/ComputeRAM_Product-Brief.pdf", "https://synthara.ai/" ] }, { "id": "pimchip-pimchip-n300", "companyId": "pimchip", "name": "PIMCHIP-N300", "companyName": "PIMCHIP", "native": "苹芯科技", "class": "SRAM compute-in-memory NPU", "category": "Digital CIM", "locus": "SRAM-CIM neural-network accelerator", "memory": "SRAM", "mode": "Digital CIM; implementation detail ND", "precision": "INT4, INT8, FP16 (product support reported)", "array": "Not publicly disclosed", "system": "Not publicly disclosed", "node": "Not publicly disclosed", "throughput": "Not publicly disclosed", "power": "Not publicly disclosed", "coprocessor": "NPU module / host integration", "scale": "Board/host integration; multi-chip scale-up ND", "software": "Vendor NPU development stack; details ND", "maturity": "Announced August 2024", "stage": "Announced", "confidence": "Secondary published launch report", "caveat": "Precision support may involve fallback or datapath sharing; physical SRAM macro bit widths have not been independently documented.", "sources": [ "https://pitchhub.36kr.com/project/1679727635550979", "https://www.pimchip.cn/list/9.html" ] } ] }