12 October 2026
Microsoft announces Maia 300
Next-generation software-defined inference/dataflow processor; 18.0 TB/s HBM4, 950 W TDP, 2027 production deployments. Keep announced and production devices separate.
Primary source ↗An academic lens on AI hardware
Beyond benchmarks.
Understand the architecture.
Explore AI accelerators by execution substrate, memory orchestration, scheduling and communication—not by company category. Compare verifiable silicon specifications, identify cacheless/scratchpad-centric machines, and track the frontier with traceable sources.
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Architecture records
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Subclasses
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Explicit local memory
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Evidence links
| Processor ↕ | Organization ↕ | Class ↕ | Memory orchestration ↕ | SRAM/cache (MB) ↕ | Off-chip (GB) ↕ | Off-chip BW (TB/s) ↕ | Power (W) ↕ | Process ↕ | Lifecycle ↕ | Compare |
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Numerical “SRAM/cache” combines a common unit for sorting only; L2/LLC cache and software-managed scratchpad are semantically different and labeled in each chip's detail view. A blank cell (—) means not disclosed or not comparable, not zero. Off-chip memory includes GDDR6 where identified. Power may describe board, package or chip TDP—compare scopes before ranking.
12 October 2026
Meta describes MTIA 300's fabric
Meta details a 51.2T Ethernet-based scale-up switch (Tahan) and 6.4 Tb/s per-accelerator interconnect for MTIA 300 systems.
Primary source ↗18 August – 2 September 2026
Spatial architectures evolve
Cerebras disclosed WSE-3T and SambaNova published its SN50 architecture deep-dive, strengthening the importance of explicit SRAM and communication orchestration.
Cerebras ↗ · SambaNova ↗Architectural classification
A1 SIMT/vector–tensor; B1 structured tensor arrays; B2 flexible tensor datapaths; C1 reconfigurable spatial fabrics; C2 distributed-memory manycores; C3 deterministic streaming; D1 model-compiled datapaths.
Dataflow, scratchpad, cacheless, CGRA-like, 3D and wafer-scale are cross-cutting attributes. Borderline industrial processors receive provisional classification notes.
Evidence & update policy
- Prefer vendor datasheets, software/architecture manuals and conference papers; cite each chip's primary URLs.
- Do not infer unavailable area, SRAM, die node, bandwidth or power from other generations.
- Never compare cache capacity with scratchpad capacity without distinguishing their semantics.
- Distinguish roadmap announcements, currently available parts and historical academic architectures.
- Revalidate changed specifications before publishing an updated snapshot.
Maintenance model
This website is intentionally static, offline-capable and inspectable. Its dataset is stored in chips.json. Edit that file and run python build.py to regenerate this standalone page. Publish to GitHub Pages, Netlify or any static host.
Weekly research alerts are separate from publishing. A monitoring report does not autonomously modify a deployed site without a connected repository and deploy pipeline.
Why not a single ranking?
Nominal FLOPS, SRAM capacity, HBM bandwidth and system power can optimize different bottlenecks. Compare at consistent granularity (die/chip/module/card/rack), specify workload precision and sparsity assumptions, and treat interconnect scale-up vs scale-out independently.
Typical missing fields: die area, NoC bisection throughput, local SRAM bandwidth, actual steady-state energy and real-world model performance.